AMD's EPYC Genoa-X Server Processor to Feature 3D V-Cache for Improved Performance

Advanced Micro Devices (AMD) is planning to reintroduce a key consumer feature to its latest server processor, the EPYC Genoa-X. According to leaked documents, the processor is set to include 768MB L3 3D cache, a technology that allows more cache memory to be allocated to the CPU core, improving its performance in specific applications, such as computational fluid dynamics, electronic design automation, and structural analysis.

The EPYC 9684X, a 96-core/192-thread processor expected to be part of the Genoa family, has more than 1.25GB of cache memory available, comprising L1, L2, and L3 cache. This is more than ten times what Intel’s top-of-the-range Xeon processor can offer, setting a new world record.

AMD is reportedly considering rolling out L4 cache in the future, which could introduce more latency and other compromises on the CPU floor plan, but would provide faster memory closer to the cores and improve performance. A 2020 patent called “Steering Tag support in virtualized environments” suggests AMD is exploring multi-gigabyte L4 cache solutions.

Cache is a critical component of modern computing, and more cache memory can improve a processor’s performance. With the EPYC 9684X featuring 96 cores and a planned 128-core version landing soon, L4 cache may come sooner rather than later. Other companies, such as IBM, have already introduced L4 cache to their processors, with the Z-series featuring 128MB of L4 cache.

AMD’s Genoa family processors are expected to have a TDP of 400W, up from 280W for current “ROME” processors and up from 360W for non-3D cache EPYC 9654 processors. Turbo speeds are expected to remain the same compared to the latter, with an increase of 200MHz compared to the 64-core EPYC 7773X.

As competition in the processor market intensifies, the addition of 3D and potentially L4 cache memory to AMD’s latest server processor provides a competitive advantage for the company. It could improve the performance of the processor in specific applications and potentially set a new standard for cache memory in the market.

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